In manufacturing the semiconductor device such as LSI, or the like, the lithography step and the subsequent etching step are performed for the purpose of processing a film such as an insulating film, a conductive film, or the like into a desired shape. In the lithography step, the resist pattern is formed by coating a photoresist on the film and then exposing/developing the photoresist. Then, in the etching step, the device pattern is formed by etching the underlying film while using the resist pattern as a mask.
An exposure time in the lithography step exerts an influence on a line width of the resist pattern. Therefore, when an error is made in setting the exposure time, a line width of the final device pattern is deviated from a target line width and in turn a yield of the semiconductor device is lowered. For this reason, in order to conform the line width of the device pattern with the target one, various managing methods of the exposure time in the lithography step are proposed.
For instance, in Patent Literature 1, from the viewpoint that a variation of a pattern dimension of the exposed and developed photoresist is increased unless a time required from the end of the prebake of the photoresist to the start of the exposure is made constant, the variation of the pattern dimension is prevented by changing the exposure conditions.
However, the exposure conditions are not changed in each chip area on the same wafer. Therefore, it is impossible to prevent the unevenness of the line widths of the resist patterns, which is caused in respective chip areas in the same plane of the same wafer.
Also, in Patent Literature 2, the exposure amount on the wafer is set differently in the concentric distribution in the lithography step, and thus dimensions of the resist patterns are differentiated deliberately between the center portion and the peripheral portion of the wafer. According to this, it is asserted that a variation of a pattern dimension of the film due to a difference in an etching rate between the center portion and the peripheral portion of the wafer can be absorbed by a dimensional difference between the resist patterns, and thus the line width of the pattern formed after the etching is made uniform in the wafer plane.
However, it can be considered that the variation in the pattern dimension after the etching is not caused only by the difference in the etching rate and such variation may be caused by another factor. Also, it can be considered that the variation is not formed in a concentric fashion by a certain factor. In that case, such a situation may be supposed that, when the exposure amount distribution is formed concentrically, the variation of the pattern dimension after the etching is far from being absorbed at a certain portion of the wafer and, rather, such variation is amplified at that portion. Thus, there is a possibility that the pattern dimension is deviated largely from the target value.
In addition, in Patent Literature 2, focuses is made only on the variation of the pattern dimension in the wafer plane, and the variation in the lot consisting of plural wafers is not considered.
(Patent Literature 1)                Patent Application Publication (KOKAI) 2001-338865 (Paragraph No. 0025)        
(Patent Literature 2)                Patent Application Publication (KOKAI) 2000-277423 (Paragraph Nos. 0015 to 0029)        